What Is High-Level Synthesis? C++ to RTL

High-Level Synthesis (HLS) is a hardware design methodology in which digital circuits are described in a high-level language — typically C++ or SystemC — and automatically compiled into register-transfer level (RTL) code such as Verilog or VHDL. Instead of hand-writing the clock-by-clock behaviour of a circuit, the designer writes an untimed algorithmic description, and the HLS tool decides how to schedule operations onto clock cycles and hardware resources under the designer's constraints.

The result is the same kind of RTL that a hardware engineer would write by hand, ready for standard logic synthesis and place-and-route flows targeting an ASIC (application-specific integrated circuit) or FPGA (field-programmable gate array).

Published: 10 July 2026 · Last reviewed: 4 October 2026 · By: Videalt Ltd.

Workflow from C++ or SystemC through HLS scheduling, allocation, and binding to generated RTL and ASIC or FPGA implementation — HLS turns an algorithm and its architecture constraints into cycle-accurate RTL; conventional synthesis and place-and-route still complete the implementation.View full-size diagram

How HLS works

An HLS compiler performs three core transformations on the input C++:

Scheduling — assigning each operation (multiply, add, memory access) to a specific clock cycle, subject to data dependencies, the clock period of the target technology, and the designer's latency and throughput constraints.
Allocation — deciding how many hardware resources (multipliers, adders, memories) to instantiate.
Binding — mapping each scheduled operation onto a specific allocated resource, sharing hardware across cycles where profitable.

The designer steers these decisions with constraints and directives rather than by rewriting code. The most important ones:

Loop pipelining — starting a new loop iteration every N cycles (the initiation interval) so the hardware streams data instead of processing one item at a time.
Loop unrolling — replicating datapath hardware to process multiple elements in parallel.
Memory mapping and banking — deciding whether arrays become registers, single-port or multi-port RAMs, and how they are partitioned to feed parallel hardware.
Interface synthesis — turning function arguments into concrete hardware interfaces: streaming channels with handshakes, AXI buses, or simple wires.

Because these decisions are expressed through code structure and constraints, one verified algorithm can produce several microarchitectures. A filter might use a resource-shared architecture for a cost-sensitive target and more parallel hardware for a throughput-sensitive target. Retargeting still requires technology-specific libraries, interfaces, constraints, and renewed optimisation.

Bit-accurate data types

Software integer types often carry more width than a hardware datapath needs, and unnecessary bits can increase area, delay, and power. HLS designs therefore commonly use bit-accurate arbitrary-precision types, such as the ac_int/ac_fixed (Algorithmic C) or ap_int/ap_fixed libraries, so a 12-bit ADC sample can remain 12 bits where the required range and arithmetic permit. Fixed-point conversion and precision analysis — choosing word lengths that meet accuracy requirements at minimum cost — is a core HLS design skill.

HLS vs hand-written RTL

Typical engineering differences between hand-written RTL and an HLS flow
Criterion	Hand-written RTL	High-Level Synthesis
Source representation	Cycle- and signal-level hardware description	Algorithm and architecture expressed in C++ or SystemC plus constraints
Functional simulation	RTL event simulation	Native compiled model for early functional testing, followed by RTL checks
Microarchitecture changes	Often require explicit RTL restructuring	Code structure and constraints can generate alternative schedules and resource mappings
Design-space exploration	Each alternative is implemented explicitly	Multiple latency, throughput, and resource points can be generated from one functional model
Retargeting	Technology-specific timing and implementation work	Re-synthesis is possible, but libraries, interfaces, constraints, and optimisation must be revisited
Cycle-exact control logic	Natural fit	Possible but often better left in RTL

HLS does not remove the need for hardware architecture or RTL sign-off skills. Good results require understanding the hardware implied by the source, constraints, interfaces, memories, and target technology—not merely writing C++ that the tool accepts.

The HLS tool landscape

Selected commercial and open-source HLS tool families
Tool	Vendor	Typical use
Catapult HLS	Siemens EDA	ASIC and FPGA; C++/SystemC; widely used in production ASIC flows
Stratus HLS	Cadence	ASIC-oriented C++/SystemC synthesis
Vitis HLS	AMD (Xilinx)	FPGA and adaptive SoC targets
High Level Synthesis Compiler	Altera	FPGA targets in the Quartus ecosystem; formerly the Intel HLS Compiler
Bambu	Politecnico di Milano	Open-source academic/research HLS
XLS	Google (open source)	Alternative HLS approach with its own DSL

Where HLS shines

HLS delivers the biggest advantage on algorithmic, datapath-dominated blocks — designs defined by mathematics rather than by protocol state machines:

Digital signal processing: FIR/IIR filters, FFTs, channelisers, beamforming
Image and video: ISP pipelines, scalers, encoders/decoders, computer vision
Wireless and wireline communications: baseband modems, FEC, equalisation
Security: cryptographic engines, hashing, compression
AI/ML: custom inference accelerators and operators

Conversely, deeply control-oriented logic with cycle-exact external protocol behaviour, and gate-level hand-optimised datapaths, often remain better served by traditional RTL — a pragmatic project mixes both.

If the boundary or expected benefit is still uncertain, use the HLS feasibility-study framework. For an existing Verilog or VHDL implementation, see the RTL-to-HLS migration guide.

Verification in an HLS flow

HLS moves a large part of functional verification to the C++ or SystemC model, where a self-checking testbench can compare the design with a trusted reference before synthesis. The generated RTL is then checked with C/RTL co-simulation and, where appropriate, equivalence methods. Standard RTL sign-off—including lint, clock/reset-domain checks, synthesis, timing, and implementation analysis—still applies. See the detailed HLS verification guide.

Frequently asked questions

Is HLS-generated RTL as efficient as hand-written RTL?

It can be competitive for suitable datapath-dominated blocks, but there is no universal result. Quality depends on the architecture, coding style, constraints, tool, target technology, and the skill of the designer. Critical designs should be compared with downstream synthesis or implementation evidence.

Can HLS be used for ASIC design, or only FPGAs?

HLS supports both ASIC and FPGA development. The target libraries, memories, interfaces, timing constraints, and downstream flow differ, so the design must be synthesised and evaluated in the context of the intended technology.

What languages does HLS use?

Mainstream commercial HLS tools commonly accept C++ or SystemC and provide bit-accurate integer and fixed-point libraries. Supported language subsets, libraries, and pragmas vary by tool, so portable algorithm code still needs tool-specific integration and optimisation.

How is an HLS design verified?

First, the C++ or SystemC model is checked with a self-checking testbench and a trusted reference. The generated RTL is then checked with C/RTL co-simulation and, where appropriate, equivalence methods. Normal RTL sign-off such as lint, CDC, synthesis, and timing analysis still applies.

When is HLS a poor fit?

HLS is usually a weaker fit for heavily control-oriented logic with cycle-exact protocol behaviour, asynchronous or mixed-signal circuitry, technology-specific structures, and blocks whose value depends on manual gate-level optimisation. Mixed HLS and RTL is often the pragmatic architecture.

How much faster is HLS than hand-written RTL development?

There is no universal multiplier. The benefit depends on the block, starting point, verification burden, tool flow, and team experience. HLS tends to help most when a team can verify the algorithm at C++ level and explore several architectures without manually rewriting RTL.

Primary sources and further reading

Related guides and services

Decision guide

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